The design of the popular turbo code interleaver is usually achieved by storing a pre-calculated interleaver addresses in a memory or an address look-up table. When an interleaver address is needed, the address may be read from the memory or the address look-up table. This approach consumes both a large circuitry area and much power. Take LTE turbo code as example. The decoding length may range from 40 to 6144 bits. For the 188 types of decoding length, the memory is required to store 188 sets of interleaver addresses of length between 40 and 6144 bits. The maximum of the storage required for 6144-bit interleaver is up to 6144×13=79872 bits.
U.S. Publication No. US2008/0115034 disclosed a QPP interleaver, applicable to a coder/decoder for turbo code. The prior art describes the algorithm for serially generating interleaver addresses. The n-th value, Π(n), of the sequence outputted by the address generator may be expressed as:Π(n)=(f1n+f2n2)mod k, n=0, 1, . . . , k−1,where Π(n) is the n-th interleaved output position, f1 and f2 are QPP coefficients, k is the information block length of the input sequence and mod is the modulus operation.
As shown in FIG. 1, control unit 106 uses a modulo-counter 108 to provide an input index n to an address generator 104 and generates a control signal 108a for inputting to address generator 104 and an interleaver memory 102 respectively to indicate whether the operation is a read operation or a write operation. The values of Π(n) calculated by address generator 104 are stored in interleaver memory 102. When interleaver address Π(n) is needed, the address is read from interleaver memory 102 serially. The calculated interleaver addresses are contention-free.
U.S. Publication No. US2002/0159423 disclosed a technique to efficiently generate memory addresses for a turbo code interleaver using a number of look-up tables. U.S. Pat. No. 6,845,482 disclosed a technique to automatically generate interleaver addresses. The turbo code interleaver uses an element for generating prime-number index information and five look-up tables to generate memory addresses of the turbo code interleaver.
The above techniques describe the theory of the algorithm, architecture and process for serially generating interleaver addresses. Most of the parallel operation techniques emphasize more on improving the performance of the parallel processing of log-Maximum a Posteriori (MAP) processor, and less on the efficient design for executing the parallel interleaving of the output from the parallel computing and storing to a memory. However, in actual hardware or circuit design, if an architecture based on parallel address generator used for decoder architecture, such as, parallel turbo decoder using a plurality of log-MAP for parallel operation, the parallel address generator may improve the output rate of the decoder.
U.S. patent application Ser. No. 12/647,394 (filed by the applicant on Dec. 25, 2009) disclosed an address generating apparatus for QPP interleaver. The apparatus is based on a QPP function Π(i)=(f1i+f2i2) mod k, inputs several configurable parameters generates a plurality of interleaver addresses sequentially via a basic recursive unit, and generates a plurality of corresponding groups of interleaver addresses in parallel via a plurality of recursive units. Based on the computation result of the interleaver address, each sequentially inputted data may be written to a corresponding memory address via a data multiplexer.